Power and Area Estimation/Optimization in Behavioral Synthesis

In order to offer better design space exploration, the HLS tool must provide the designers a way to investigate diverse interconnection schemes. Little works reported on mixed bus and mux architectures. Cathedral-II [2] has a restricted bus-mux interconnection model, where interconnections inside EXU’s are mux-based and global connections are busbased. In general, mux-based interconnections are more efficient for resources with low sharing factors. Contrarily, designs that employs a large controller or a large interconnection set to enable high resource sharing factors give better results with bus-based interconnections [3]. However, like in Harvard architecture with contrast to Von Neuman architecture, maximum sharing of busses and functional units may not guarantee lower power solution. Thus, the problerm is to how to estimate power consumption due to switching activities related with both mux and bus.